| 1 | Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation | Scientific Reports | 14,1 | 01/Dec | 2024 | View |
| 2 | FPGA Implementation of Proficient Vedic Multiplier architecture using Hybrid Carry Select Adder | International journal of electronics | 111,8 | 1253-1265 | 2023 | View |
| 3 | FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier | International journal of electronics | 110,4 | 587-607 | 2022 | View |
| 4 | Design of Proficient Two operand adder using Hybrid Carry Select adder with FPGA implementation | IETE journal for research | 69,12 | 9152-9165 | 2022 | View |
| 5 | High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation | IETE journal for research | 69,5 | 2301-2309 | 2021 | View |
| 6 | Solar Powered Autonomous Robotic Car Using for Surveillance | Intelligent Manufacturing and Energy Sustainability | 265 | 249-256 | 2021 | View |
| 7 | Design and FPGA Implementation of Efficient Multiplier Architecture using Reversible Logic | WSEAS Transactions on Signal Processing | 21 | 51-58 | 2025 | View |
| 8 | Investigation on Power, Delay and Area optimization of XOR Gate | WSEAS TRANSACTIONS on CIRCUITS and SYSTEMS | 19,32 | 297-304 | 2020 | View |
| 9 | Proficient Architecture for Vedic Multiplier using Various VLSI Design Techniques of Optimized Adder | International Journal of Computer applications | 184,50 | 15-21 | 2023 | View |
| 10 | A Review on Image Enhancement Techniques using Modified Approach of Histogram Equalization | international journal for research & development in technology | 13,5 | 188-193 | 2020 | View |
| 11 | A Novel Technique to Preserve Nourishment of Food Beverages using E-Nose Technology in Food Industry | International Journal for Scientific Research & Development | 8,2 | 1284-1288 | 2020 | View |
| 12 | Efficacious Convolution and Deconvolution VLSI Architecture for Productiveness DSP Applications | International Journal for Science and Advance Research in Technology | 2,9 | 117-122 | 2016 | View |
| 13 | An Efficient VLSI Architecture for FIR Filter using Computation Sharing Multiplier | International Journal of Computer applications | 54,14 | 01/Jun | 2012 | View |
| 14 | DWT/IDWT processor for power line communication system | Elixir International Journal | 50 | 10434-10439 | 2012 | View |
